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ASIC Verification Engineer - System Verilog


Last Updated: 7/04/21

Job Description

Dear Job Seekers,

Moschip is Hiring for:

Job Title: ASIC Verification Engineer - System Verilog

Job Description:

  • ASIC Verification Engineer Required Skills Strong SV/UVM fundamentals Experience of building Test benches from scratch.
  • Assertions driven verification Coverage driven verification AXI/AHB protocols Power aware verification is plus.
  • Good to Have Experience in verification in the areas of CPU verification.
  • Python scripting Responsibilities Should be able to develop the entire unit level test bench in SV using UVM from scratch.
  • Need to Develop the Test plans for a given feature by understanding specifications/interacting with RTL designers.
  • Need to develop the SV tests as required as per the Test plan.
  • Need to develop the assertions/checker as required.
  • Need to develop the complete coverage for a given feature and should be able to close it with sign-off metrics.

Experience: 3-6 years

Salary: As per the Company Standards

Location: Bangalore

Company Details

Hyderabad, Telangana, India