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Verification Engineers


Last Updated: 9/02/21

Job Description

Dear Job Seekers,

Our Client is Hiring for:

Job Title: Verification Engineers


1.UVM and System Verilog.
2.PCIe Gen 3 and Above
3.Knowledge of TL, DL, PL Transaction Sequences
4.Knowledge of LTSSM will be good
Test Bench Development and Functional Coverage Closure

Experience: 3-12 years

Salary: As per the Company Standards

Location: Hyderabad

Company Details

Hyderabad, Telangana, India